Outlook Supplement - Flipbook - Page 16
Forecast
— will come from heterogeneous 3D
integration. GaAs optimizes linearity for
front-end amplification; GaN delivers
high power density; silicon excels
at complex control and digital logic.
Instead of placing these dies next to
one another on a board, 3D integration
stacks and vertically interconnects them
using technologies such as system-inpackage (SiP), through-silicon vias
(TSVs), and advanced interposers.
The benefits are real and measurable:
• Greater interconnect efficiency:
Microscale vertical vias replace
millimeter-long traces, cutting
interconnect power consumption by
30–50 %.
• Significant SWaP reduction: A
stacked 3D RF module can shrink
system footprint by 60% or more—a
vital advantage for satellites and
beamforming arrays.
• Improved signal quality: Shorter
electrical paths reduce insertion
loss and noise, boosting overall link
performance.
This trend validates Circuits
Integrated’s focus on tightly integrated
GaAs antenna-in-package (AiP)
solutions. While GaAs remains the superior choice for high-efficiency, linear
amplification in dense phased arrays,
its full potential is only unlocked when
it is tightly integrated—vertically—
with silicon control layers. In the race
toward 2026 and beyond, success
won’t come from the best standalone
transistor: it will come from the best
architected, vertically integrated RF
system. The era of discretes is giving
way to the era of 3D integrated RF.
Transitioning Advanced
Packaging From “More Moore”
to “More than Moore”
GUIDO UEBERREITER, V P
S emiconduc tor Str ategy,
VON ARDENNE
For decades, the semiconductor
industry has pursued a clear objective:
to integrate as many functions as
14
possible into a single sysOf course, economics
tem-on-chip (SoC). By scaling
need to benefit as well. The
transistors from millions to trilindustry transitioned from
lions on a single die, the “More
wafer-level packaging to
Moore” large-scale integration
panel-level packaging to
approach delivered remarkable
improve cost-efficiency.
technical and economic benSimilarly, heterogeneous
efits, leading to technologies
integration offers an opthat enabled the PC, mobile
portunity
to combine chips
GUIDO
phone, and the early stages of
from
different
wafer sizes
UEBERREITER
artificial intelligence (AI).
and technology nodes and
Over time, it became obvious that
place them as close together as possible
not all functions on the SoC benefit
within a single package to maximize
from scaling in the same way. New
performance and yield.
megatrends require optimization on
VON ARDENNE’s equipment
all fronts: the compute cores, memory
portfolio is well positioned to support
subsystems, interfaces, as well as the
these advanced packaging roadmaps in
power supply infrastructure.
2026 and beyond. From cluster-based
Today this shift is most visible in
systems for wafer-level packaging,
high-performance compute, where
to panel-level equipment for larger
we are witnessing a de-integration of
package formats—VON ARDENNE
monolithic SoCs and replacing them
enables high throughput, uniform, and
with heterogeneous, chiplet-based
scalable deposition and processing.
architectures. Functions that were once
These solutions support the ability to
distributed across printed circuit boards create and fill nanometer-level strucand discrete packages are now brought
tures, regardless of substrate size or
into close proximity within a single
type, ensuring flexibility and quality
advanced package to deliver higher
as packaging architectures continue to
bandwidth, lower latency, improved
evolve.
power efficiency and better cost control.
“More than Moore”— value created
Advanced Packaging to Continue
by integrating diverse functions and
Making Major Strides in 2026
technologies into a single package—has BYRON EXARCOS, C E O ,
been critical to the performance and
C l a s s O n e Te c h n o l o g y
cost efficiencies that enable AI to scale
As the industry moves into 2026,
today.
advanced packaging remains one of the
In 2026, we expect to see this
strongest engines of growth and innoarchitectural transition expand beyond
vation across the global semiconductor
compute. High-end radio frequency
landscape. Demand continues to accel(RF) components will be co-packaged
erate across AI, data center, photonics,
with data processing companion chips,
and defense applications, creating persimilar to what we have been doing
sistent pressure for higher-performance
for decades with camera and image
interconnects, more
sensor solutions. Similarly, we will see
precise metallization,
power semiconductors being integrated
and tighter process inwith logic chips for better efficiency
tegration. These trends
and system response. Photonic intedirectly align with
grated circuits (PICs) will be packaged
ClassOne Technology’s
together with data processing chips to
core strengths in adovercome electrical interconnect limits
vanced plating, surface
BYRON EXARCOS
for better signal integrity.
preparation, and wet
| Supplement to January 2026 Semiconductor Digest
www.semiconductordigest.com
