Outlook Supplement - Flipbook - Page 18
Forecast
“AI factories” is changing how devices
are designed, assembled and validated.
These changes are elevating the role of
semiconductor testing, in an ever-increasing quest to improve yield and reliability, and accelerate time-to-market.
The year ahead
Today’s AI products pack together
several compute die, fast I/O, networking interfaces, and multiple stacks
of high-bandwidth memory. With so
much silicon in one package, a single
weak die can compromise the entire
module. That’s why test has spread to
more points in the manufacturing flow — at
the wafer, at singulated
die, on the module,
and increasingly at the
board and system level.
Known-good-die is
SHANNON POULIN really the best way to
protect the investment
that is being made in these advanced
packaged products.
The second trend we’re seeing is
power. AI devices are now brushing
past a kilowatt, many will be exceeding
2kW soon, and there are plans for >4kW
products on the horizon. Entire racks
can push toward the half-megawatt
mark. Test systems must deliver that
power while keeping devices safe,
stable, and thermally controlled. As the
industry shifts toward direct-to-chip
liquid cooling, and begins to explore
immersion, test equipment will need
new ways to manage heat and replicate
real-world operating conditions.
Lastly, new technologies like silicon
photonics and co-packaged optics are
pushing the capabilities of these new
architectures. Bandwidth demands are
rising so quickly that optics are moving
closer to the compute die itself. In 2026,
we’ll see the early stages of real commercial deployment: small runs at first,
but meaningful ones. This transition
introduces new test needs that span
both optical and electrical domains,
16
from photonic wafer measurements
to system-level optical checks once
everything is assembled.
Across all of this, one theme stands
out: test capability must scale as quickly
as the devices it supports. Modular
platforms that can be upgraded for new
interfaces, higher power, or optical
workflows will help keep AI programs
on pace. In the year ahead, test will
be an integral component in ensuring
the quality and yield of devices that
are exponentially more complex than
anything we’ve seen before.
investments in next-generation packaging technology, such as chip-onwafer-on-substrate (CoWoS), EMIB,
through-silicon vias (TSVs), and
co-packaged optics (CPO). HBM and
other advanced memory technologies
also rely on 3D stacking to offer the
high processing speeds needed to fuel
AI applications.
The increasingly complex architecture of 2.5D/3D chips presents
various challenges during test. For
example, heightened density and
processing speeds elevate temperatures, increasing the risk of failure
AI Looms Large as Test
after wafer-level and final test. This
Applications Continue to Broaden
necessitates specialized test equipment
with sophisticated thermal-management
DOUG LEFEVER,
Representative Director
capabilities and active thermal control.
and Group CEO, Advantest
We foresee a growing need for more
Corp.
testing at the singulated-die level,
The semiconductor industry is entering
where more precise thermal control can
a new era in which complexity, cost,
be achieved to capture failures before
and performance pressures converge.
stacking and ensure only known-good
Meeting these demands will require
die are packaged.
unprecedented collaboration across
In addition to die-level test, custhe supply chain. In 2026 and beyond,
tomers are looking for more ways to
collaboration will be key to pioneering
reduce yield loss, especially as the
best-in-class test cells that drive velocity cost of 3D packaged devices rises. In
and innovation.
response, test companies are
From a market perspective,
moving more test content
we see artificial intelligence
to earlier insertions. For
(AI) continuing to drive
example, much of the speed
significant growth in the
and performance testing that
semiconductor market,
used to be reserved for final
spurring new innovations
test is now being performed
in advanced packaging,
at wafer sort or singulated
DOUG LEFEVER
high-bandwidth memory
die test to ensure that the
(HBM), thermal control, and
die can perform high-peroptical integration to support the next
formance workloads before they are
generation of high-performance GPUs.
packaged.
As these complex challenges combine,
We are also beginning to see systesting plays a key role in enabling
tem-level test content being combined
customers to meet time-to-market and
with other test insertions, enquality requirements.
suring better test coverage throughout
In the coming year, we anticipate
the back-end flow. We expect all
continued advancements in 2.5D/3D
of these trends in test to continue
packaging to enable higher perforinto 2026 as customers seek ways to
mance in AI and high-performance
reduce yield loss and cut costs, and we
computing (HPC) devices. Foundries
look forward to seeing what the year
and OSATs are making significant
ahead will bring.
| Supplement to January 2026 Semiconductor Digest
www.semiconductordigest.com
