Outlook Supplement - Flipbook - Page 23
Forecast
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Advanced Packaging:
The Top Enabler
BOB PATTI, F o u n d e r a n d C E O ,
NHanced Semiconductors
In 2026, I expect advanced packaging to
continue its growth as the industry’s top
enabler. More-than-Moore is the future
and advanced packaging is key. Three
areas of advanced packaging where
I foresee major advances are die-towafer hybrid bonding, photonics, and
interposers.
Die-to-wafer
hybrid bonding
New technologies allow
high speed die-to-wafer
hybrid bonding with
ultra accurate overlay,
thereby reducing
BOB PATTI
cost and increasing
throughput, erasing
the advantages previously held by
wafer-to-wafer bonding. We have also
seen steady improvement in known
good die (KGD) approaches. Together,
these two advancements have pushed
component manufacturers to create
their own chiplets for next generation
devices. Bonded interconnect is 100x
denser and 100x lower power than
soldered connections. Die level hybrid
bonding has not yet gone mainstream,
but the path seems clear: 2026 will see
further chiplet enablement and large
scale prototyping to prove that hybrid
bonding is ready. By 2028-2030, I
predict high volume manufacturing of
hybrid bonded chiplets.
Photonics
Photonics continues its steady progress
toward usage both in-package and
package-to-package. Optical EIC and
PIC integration and laser attachment
are already commonplace; however,
fiber attachment is still labor-intensive
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and relatively low volume. Optical
interconnect is the obvious solution for
the ravenous bandwidth needs of AI
and HPC, but there is no high-volume
manufacturing method for adding a
thousand fibers to a module. The key
breakthrough required is silicon level
connectorization of optical interconnect.
Solutions are already being tested and
might debut in the coming year. When
ready, new connectors will trigger rapid
evolution in machine architectures and
data centers.
The next “coming of age” for
photonics will be high density optical
circuits to support the new, massively
parallel optical interconnects. Fueled
by silicon photonics advancements and
intimate incorporation of new materials like GaN and TFLN, commercial
products with true ≤1 pJ/bit are at hand.
First commercial shipments may take
place in 2026.
Interposers
Interposer size has been limited to 3.3
reticles by the CTE mismatch between
silicon interposers and the organic
substrates they are assembled on.
Nonetheless, we see increasing demand
for larger interposers. Glass interposers,
with their higher CTE, are poised for a
market breakthrough to fill this need.
Glass interposers with sizes greater than
10 full reticles are coming – perhaps as
early as 2026.
Building Differentiated Advanced
Packaging Solutions and
Scaling Chiplet Production
JIM STRAUS, V P o f S a l e s , A C M
Research
As the semiconductor industry enters
2026, a strong transition is anticipated,
with advanced packaging firmly
established as a critical engine of
innovation. Artificial intelligence (AI)
and high-bandwidth memory (HBM)
workloads will continue to drive device
sizes, interconnect density, and power
budgets, forcing an accelerated shift
from traditional wafer-based processes
toward glass substrates and 3D stacking.
Throughout this transition, chiplets will
remain a central focus. However, the
industry’s focus will also broaden from
what we integrate to how and where we
build devices, with wafer-level packaging (WLP) and panel-level packaging
(PLP) both playing crucial roles.
WLP is expected to continue growing
as the production standard for 3D integration, headlined by its use in AI and
HBM devices on 300mm wafers using
silicon interposers. At the same time,
PLP is emerging as the next lever for
cost reduction and capacity expansion.
According to Yole’s 2025 PLP report,
the PLP market is projected to reach
$600 million by 2030, with a CAGR of
27% from 2024 to 2030. This growth is
primarily driven by its cost advantages
and higher area utilization, simultaneously
meeting the technical
requirements of both
advanced and traditional packaging.
By delivering
significant cost savings JIM STRAUS
and achieving substrate
utilization beyond 80%, high-end
fan-out panel-level packages (FOPLP)
and 2.5D interposer technologies are
projected to drive AI, HPC, mobile, and
high-end consumer markets. Enabled
by equipment innovations, the evolution
from round wafers to square glass
panels will also allow for more dies per
substrate, higher throughput, and better
economics for increasingly complex
packages. Increasing investments from
equipment and material suppliers will
go toward building a comprehensive
ecosystem that meets customer needs.
For all its benefits, this transition will
not come without challenges. As panel
sizes adapt from roughly 310 x 310mm
to 600 x 600mm and beyond, a lack of
standardization is expected to raise both
R&D and capital costs for OSATs, fabs,
and equipment vendors. Developing
Semiconductor Digest Supplement to January 2026
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